A 2.5–5GHz Injection-Locked Clock Multiplier with Embedded Phase Interpolator in 65nm CMOS

We present a wide-range ring oscillator based injection-locked clock multiplier with an embedded phase interpolator. The pseudo-differential ring oscillator employs current-starved inverters with a tunable capacitor load. The inverter delays are controlled to change the output phase while retaining the output frequency and jitter. Designed in a 65nm CMOS process, the clock multiplier uses a 312.5MHz reference clock and generates a 2.5–5.0GHz output clock when simulated with RC-extracted parasitics. The output clock phase can be controlled with 1.5° − 2° accuracy. At 5GHz output, the clock multiplier achieves an integrated rms jitter of 450–550fs across phase interpolation codes. Operating from 1.2V supply, it consumes 9.4mW at 5GHz that scales down to 4.3mW at 2.5GHz.