Low-power and Area Efficient Approximate Multiplier with Reduced Partial Products

Need of approximate computing has increased to the pinnacle for error-tolerant applications. This leads to further optimization in terms of power and area with remarkable enhancement in computational speed within an acceptable error range. So, the performance and the error characteristic are considered with equal importance. This work presents a power and area optimized architecture for error-tolerant multiplier. A trade-off is made with the error characteristic by using approximation at the lower stage of partial product. Results for area, power and error factor are shown for range of multipliers. A significant improvement is achieved by using the proposed technique. The logics are implemented using 45nm process technology and Cadence GENUS™ Synthesis Solution. The synthesis environment is set to slow_vdd1v0 at operating conditions PVT_1P1V_0C (balanced tree).