High Precision Binary Coded Decimal (BCD) unit for 128-bit addition

Financial and business applications utilize decimal information and invest the majority of their energy in decimal number-crunching. Programming usage of decimal number-crunching is common, at any rate, multiple times slower than paired math actualized in equipment. This paper proposes a reduced delay binary coded decimal (BCD) adder that improves BCD addition delay by expanding parallel processing. The ordinary BCD adders are delayed because of the utilization of two binary adders. we structured and executed a new double mode BCD adder which utilizes just a single adder that produced the sum and sum+6. Using a pipeline procedure, an additional 128-bit BCD adder was implemented. The proposed BCD adder was planned and implemented using VHDL with XILINX 9.2 modification. The sequences of the regular BCD adder contrast with the proposed BCD adder. Experimental results show that the proposed BCD adder is 16.7% quicker than a traditional BCD adder. The proposed BCD 128-bit adder is 61.2% faster than the regular BCD 128 adder.