Designing Printed Circuit Boards to Drastically Reduce the Occurrence of Tombstoned Components

Electronic components continue to shrink as electronic printed circuit boards become denser. Smaller discrete passive devices such as surface mount capacitors and resistors are increasing in use and approaching sizes that require magnification to recognize. Unfortunately, during the Surface Mount Technology (SMT) assembly process these smaller devices are the primary source of defects during soldering. One of the leading defects during SMT is “Tombstoning,” a condition where a capacitor or resistor only solders on one end due to vertical rotation of the component creating an open circuit. Rework is costly and potentially induces additional factors that can decrease overall reliability because rework requires heating the defect location multiple times with a soldering iron; once to remove and once to replace for each pad. This defect can be drastically reduced by using the correct printed circuit board design parameters when laying out the board pad geometries. Printed Circuit Board pad size and geometry play a significant role in reducing and eliminating “tombstoning.” This paper presents the results from a comprehensive Designed Experiment illustrating the effects of different pad designs and their effect on the amount of defects. The results show that smaller pad geometries are a major factor in the reduction of “tombstoning.” This combined with the elimination of solder mask between the pads yield significant reduction in SMT soldering defects. This paper will delineate the major factors involved and how a comprehensive Design of Experiment (DOE) was planned and performed to drastically reduce this type of defect.