Validating and Characterizing a 2.5D High Bandwidth Memory SubSystem

High Bandwidth Memory (HBM) Dynamic Random Access Memory (DRAM) has emerged as a preferred choice for leading-edge graphics, networking and highperformance computing applications. HBM is also finding usage in artificial intelligence (AI), machine learning (ML) and other advanced applications that demand high bandwidth and high power efficiency. HBM systems are implemented in 2.5D technology in which the memory stack and System-on-Chip (SoC) are integrated using a silicon interposer in a single package. Unlike conventional Double Data Rate (DDR) systems, the memory channel in 2.5D HBM systems are not accessible outside the package, posing multiple challenges in post-silicon characterization, system validation and SoC bring up. This paper discusses the functional at-speed test challenges and solutions using IEEE1500 based test structures implemented in the PHY, complementing those in DRAM. The paper also discusses a novel method to allow channel pin access for receiver and transmitter characterization with minimal impact to normal operation. Silicon results are presented at different levels of system hierarchy that consists of Memory Controller (MC), Physical Layer (PHY) and DRAM. Together, these results demonstrate excellent test coverage of the complete HBM memory subsystem and efficient silicon debug support.