Design and Implementation of Pulse Compression Radar Waveforms Digital Generator and Processor with Real Time Side-lobes Suppression Optimum Filter on FPGA

Side-Lobes Suppression (SLS) in Pulse Compression (PC) radar aims to overcome the main problem of PC techniques, which is the high sidelobes level at the Matched Filter (MF) output. Thereby, enhances the overall detection performance of the radar system. Recently, a generic side-lobes suppression Optimum Filter (OP-F), following the MF, for complete cancellation of these range-time sidelobes for any phase coded waveforms in PC radar has been introduced. Implementation issues of such side-lobes reduction or cancellation filters have not been exploited in any other literature before. In this paper, real time digital design and implementation of this OP-F on Xilinx Virtex-6 Field Programmable Gate Array (FPGA) platform is presented. The implemented design is divided into two parts; part 1 includes digital waveform generator of two different phase coded signals (binary Barker and polyphase (P4) codes each of length 13). Part 2 is the generated waveforms digital matched filter followed by the generic SLS OP-F. Moreover, verifying both of theoretical and experimental results along with implementation resources is presented. The results targeting the FPGA platform show that the proposed implementation has achieved complete matching between both theoretical and experimental analysis. The implemented SLS OP-F achieves the expected enhancement without any extra hardware complexity.