Research on Package Thermal Resistance of Power Semiconductor Devices

Power electronics is becoming more important than before with motor application expansion. For size reduction of inverter integrated motor design, accurate temperature prediction of power devices is becoming critical. For up to several hundred-watt motor system, inverter is designed with discrete power devices with standard package. This paper investigates package thermal resistance of a DPAK package as an example. Firstly, three-dimensional heat conduction simulation only with DPAK package model is conducted. It is found that its package thermal resistance changes by $\sim 6.2^{\circ}\mathrm{C} /\mathrm{W}$ due to boundary condition variation. After that, simulation not only with DPAK package but also with PCB is conducted to understand package thermal resistance of a real system implementation case. It is found that package thermal resistance is $\sim 2.4$ to 2.6°C/W with smallest copper patterns, while its value is $\sim 1.1$ to 1.2°C/W in the case that copper fully covers board as “layer”.