Hardware Implementation of Blind Source Separation Algorithm Using ZYBO Z7& Xilinx System Generator

Blind Source Separation (BSS) is termed as the extraction of source signals from mixed data without or with little knowledge about the source signals. It is used in many fields of research such as military, medical and industry. Among the many challenges that must be overcome to apply BSS to a real system, implementation restrictions are the most difficult. Software implementations require a significant amount of overhead to make them applicable to real-time systems and have a lower maximum speed of operation than hardware implementations. When speed is desired, the algorithm should be implemented on specialized hardware such as a Field Programmable Gate Array(FPGA) which allows the user to take advantage of parallel computational abilities. This paper describes the methodology for implementing real-time DSP applications on FPGA and the concept of hardware software cosimulation of the Second Order Blind Identification (SOBI) algorithm using MATLAB Simulink and Xilinx System Generator (XSG). Performances of efficient architectures are implemented on FPGA ZYBO Z7 Zynq-7020.