Fast BCH 1-Bit Error Correction Combined with Fast Multi-Bit Error Detection

In this paper, an error correction is combined with additional detection using a BCH code. It is shown that a fast 1-bit correction can be efficiently combined with fast BCH multibit detection for all up to (2T-1)-bits errors, where T can be specified. In the case of an error, the syndrome is calculated and both a speculative 1-bit correction and an error detection process are started in parallel. The proposed error detection process checks if the actual error syndrome components contradict the 1-bit error assumption. The corresponding determinants for 2-bit to T-bit errors are computed in ascending order up to the first determinant indicating an error larger than 1-bit. This differs from the classic approach where a sequence of corresponding determinants containing syndrome components in descending order from T to 2 is computed. For the classic approach, the first determinant not equal 0 in descending order indicates the number of errors. The presented approach allows to speed up the detection by simplifying the determinants using the results of previous iterations. Under the assumption of a 1-bit error, the determinants can be simplified to a constant size. The proposed approach speeds up the error detection considerably. This method is useful for error detection and error correction in safety critical applications where 100 percent of the multi-bit errors up to a certain multiplicity have to be detected.