Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization

The ever-increasing functionality of modern electronic systems and reduced time-to-market constraints have significantly altered the typical design flow. One possible solution to deal with this rising complexity is to increase the level of abstraction toward the Electronic System Level (ESL). At the ESL, modeling system as a Virtual Prototype (VP) using SystemC and its Transaction Level Modeling (TLM) framework has become an industry-accepted solution in the last decade. VP design exploration, analysis, debugging, and integration of ever-changing functional requirements can be made faster, more accurate, and errorless with the help of a strong design understanding method. This paper presents a comprehensive automated design understanding methodology that enables designers to trace detailed information related to the VPs structure and behavior. The proposed methodology includes three main phases which are data extraction, analysis, and visualization. Experimental results including a real-world VP-based system show the advantages of our methodology such as its accuracy and applicability.