High Level Modeling of Memristive Crossbar Arrays

Crossbar architecture is one of the prominent candidates to enable memristor based in-memory computing. Recent literature suggests that predominantly SPICE level simulations have been performed to check the correctness of the memristive systems. Though SPICE simulation gives accurate results, it takes a substantial amount of time as circuit complexity increases. Currently, memristor mapping tools (such as SIMPLER MAGIC) are not guaranteed to generate a correct design by construction as they do not provide any formal proof for their corresponding tools. The aforementioned reasons motivate us to come up with a behavioral model of the memristive system. We use two processes to model the memristor-one to decide the final signal value when multiple sources drive it. Another process decides the final states of the memristors. The proposed model along with the control voltage sequence and initial states of memristors allows us to quickly verify the functionality of the memristive system using VHDL based simulation. While several SPICE level models are available, to the best of our knowledge, this is the first work that proposes a behavioral VHDL model of memristor. To validate our proposed approach, we compare our model with a SPICE based model in terms of functional correctness and runtime speedups, experimental evaluation on thirteen (13) different combinational benchmark circuits resulted in runtime speedups of 140X on average with 8X-205X range.