Area and Energy-efficient Approximate Distributive Arithmetic architecture for LMS Adaptive FIR Filter

A novel approximate DA architecture is proposed for adaptive FIR filter. LMS algorithm is used to update the weights of the filter. In this architecture we combined the CSD number and DA technique to improve the area and power efficiency of the filter. LUT-less DA computation is done. Instead register-based DA computation is used. Wallace tree adder is used to add the partial products which increase the speed and decrease the complexity of the filter. The proposed structure is coded in VHDL and simulated, synthesized and implemented in Virtex FPGA device. The device utilization report of the structure proves that the area and power efficiency is improved than the previous designs.