A New Hardware Approach to Self-Organizing Maps

Self-Organizing Maps (SOMs) are widely used as a data mining technique for applications that require data dimensionality reduction and clustering. Given the complexity of the SOM learning phase and the massive dimensionality of many data sets as well as their sample size in Big Data applications, high-speed processing is critical when implementing SOM approaches. This paper proposes a new hardware approach to SOM implementation, exploiting parallelization, to optimize the system’s processing time. Unlike most implementations in the literature, this proposed approach allows the parallelization of the data dimensions instead of the map, ensuring high processing speed regardless of data dimensions. An implementation with field-programmable gate arrays (FPGA) is presented and evaluated. Key evaluation metrics are processing time (or throughput) and FPGA area occupancy (or hardware resources).

I. Introduction

A Self-Organising Map (SOM) neural network is an unsupervised algorithm widely used for applications that require data dimensionality reduction and clustering [1], [2]. According to [3], application areas such as medical, telecommunications, robotics, Internet of Things (IoT), video and image processing are among those that use SOM. However, the complexity of SOM training phase and the large amount of data necessary, make SOM implementations difficult for high processing speed applications [4], [5].