Design and Verification of High-Speed Radix-2 Butterfly FFT Module for DSP Applications

Digital signal processing (DSP) processor is a key element of 4th Generation (4G) communication and Fast Fourier Transform (FFT) is an important operation of the modern Digital signal Processor (DSP). This work design an area and speed optimized FFT module for the DSP processor. Real-time computation of signals must meet real-time scenarios and highly requires to make computation faster as possible, hence a fast FFT proposed. Two types of methods can be used for FFT operation: first is Decimation in time (DIT) and second is Decimation in frequency (DIF). The operational speed of these algorithms depends on the multipliers used for computation. Multipliers in the FFT process are the key factor for the speed performance and if multiplier modifies in terms of area and speed overall FFT processor also performance gets an increase. This work design FFT processor with Vedic multiplier and new semi-pipelined Fast Fourier transform (SPFFT) with modified multiplication arrangement gave a provide area optimized hardware architecture. In conventional method, radix-2² had been used only for single-path delay feedback architectures. Later with many types of research works radix, 22 was extended to multipath delay commutation (MDC) architectures. This work design is provided for parallel operation of value 16 signal samples, Xilinx Vivado EDA is used for the implementation of this work. for emulation Zynq-7 FPGA board used.