Implementation of Efficient Modulo 2nAdders for Cryptographic Applications

In this brief, modulo 2ⁿ adders are presented based on different parallel prefix adders for 16, 24, 32, 48 and 64 bits. AT and AT² are the two different performance parameters considered to evaluate area-delay trade-offs. VLSI implementations shows that modulo adder based on Kogge-Stone tree has delay improvement in the range of (8.8-87) % than other adders at a cost of increased hardware by (26-68) %. Han-Carlson adder achieves better compromise between chip-area and computational delay. It is also shown that large fanout significantly effects the delay performance.