Implementation of Hybrid LBIST Mechanism in Digital Circuits for Test Pattern Generation and Test Time Reduction

Due to the increase in the amount of logic in the circuit with increase in the design technology, the complexity of the circuit structure also increases. During manufacturing, there is a possibility for faults to arise in the circuit. So, it is necessary to perform structural testing on the circuits to ensure that the circuit is not faulty. Due to the large complexity in the designs, it is difficult to test every net in the circuit and hence the Automatic Test Equipment (ATE) test time also increases. To decrease the ATE test time, several testing mechanisms are proposed to test the circuits for different sets of faults. Traditional scan method is mainly used to test the circuits. In this paper, a hybrid Logic Built In Self Test (LBIST) test methodology is proposed for testing the circuits. Stuck-at faults and Transition faults are analyzed by performing stuck-at testing and At-speed testing. Experimental results show that the implemented mechanism is helpful for diagnosing the fault locations and improving the test time.