Multiplexer Based Logic Gates Design Using Ballistic Deflection Transistors

In this paper, multiplexer based logic gates design is presented using ballistic deflection transistor. The three-parameter gaussian peak analytical model is integrated into behavioral modeling in the Verilog-AMS module to achieve the characteristics of ballistic deflection transistor. Also, the device is modeled and simulated on the Cadence AMS simulator and further the single ballistic deflection transistor is used to design the inverter/buffer circuit. The two ballistic deflection transistor is used to design the logic gates, which are based on the 2:1 multiplexer structure. The simulated results confirm the correct working of all logic gates.