Physical Implementation of Shift Register with respect to Timing and Dynamic Drop

In this paper, it is shown how partitioning, placement, and routing of an 8-bit shift register circuit using cadence tools done. The functionality of the shift register circuit is verified by writing a Verilog code and simulated using the Cadence NCLaunch tool. The RTL code is synthesized to convert the gate-level netlist using the Genus tool from Cadence. Reporting the power, area & timing of the gate-level netlist. The generated gate-level netlist is used for placement and routing in the physical design process. The placement and routing of the shift register circuit are carried out in the Cadence Innovus tool using the 180nm library file. Reporting power, area, and timing at each stage of Pre-CTS, Post-CTS, and post-routing of the circuit and GDS II file is generated. In Post-CTS the overall Power is abridged to 12.69mW, Area is 119.7504um^2 and timing is 9787ps.