Cell Weighting and Gate Inductive Peaking Techniques for Wideband Noise Suppression in Distributed Amplifiers

This paper presents a noise suppression method to improve noise figure (NF) performance of a distributed amplifier (DA) in a broad frequency range. In the proposed DA topology, the input matching resistor, which remarkably increases the NF, is replaced by a common-gate (CG) stage. The noise contribution of the CG terminating network is suppressed by employing a cell weighting plan in conjunction with a gate-inductive peaking technique. Analytical methods and a circuit implementation in a
$0.18~\mu \text{m}$
CMOS technology verify that the proposed noise suppression technique provides lower NF compared with the conventional DA (CDA) topology in the entire frequency range. This is in contrast to other reported low-noise DA topologies which decrease the noise contribution of the input matching element only in a limited range of frequencies. The measurement results demonstrate an average gain of 9.5 dB in 1-20 GHz frequency range, a noise figure less than 4 dB and 5.8 dB up to 16 GHz and 20 GHz, respectively, and an average IIP3 of 5.3 dBm. The chip occupies an area of 1.2 mm
²
, including pads, and consumes a current of 24 mA from 1.8 V supply.