A 2.75 Gb/s CMOS clock recovery circuit with broad capture range

A dual-loop PLL clock-recovery circuit uses a digital search algorithm to increase capture range with no external reference. A 0.25 /spl mu/m CMOS circuit has 350 MHz capture range around 2.7 GHz, and 5.1 ps rms jitter consuming 50 mW from 2.7 V.