Design and Implementation of High-Speed Transmission Link Based on PCI-E

In order to accomplish real-time control and monitor of high-speed acquisition system, reliable transmission of large-capacity data is in highly demand. In this article, a practical design of transmission link based on Rocket IO, PCI Express (PCI-E) and DDR3 is proposed. To counteract the data loss caused by PCI-E interrupts, large-capacity dynamic First Input First Output (FIFO) has been designed with the aid of DDR3. Cross-chip transmission link is introduced with the self-designed GTX/GTH interfaces. Besides, the design of PCI-E Direct Memory Access (DMA) mode is also demonstrated. Simulations and hardware tests are performed with the aid of Xilinx 7 series FPGAs to verify the practicality and reliability of the proposed transmission link. Quantitatively, data could be uploaded to user interface correctly at the rate of 6Gbps (approximating to the maximum rate of GTX when single lane is considered) without any loss, which means the adverse effect of PCI-E interrupts could be eradicated, and the transparent control and monitor of high-speed acquisition system could be realized with the aid of the proposed transmission link.