Performance Investigation of 2:1 Multiplexer using 90nm Technology Node for Low Power Application

This paper list low power, high-speed design of multiplexer and also examines the output of different 2: 1 MUX designed by a distinct type of logic style at 90nm technology node. It also compares delay, average power dissipation (which includes both leakage power dissipation and dynamic power dissipation) and PDP (Power delay product) of 2:1 MUX which gives a better response. This analysis will give the finest CMOS logic style which will be efficient for low power applications. The main aim is to improve digital circuits in power, delay and area domain. There are many applications of MUX in digital circuits devices. If MUX is showing better performance in power, delay and area, then the complete circuit will work efficiently.