Low Power CMOS Negative Body Biased Double-tail Latched Comparator for ECG Applications

Power consumption is one of the most important aspects for monitoring cardiac signals. Dynamic latched comparators in analog to digital converter play a vital role in power consumption. The main contribution of power consumption will explore the various performance variable like power, delay and product of both. This paper presents a double-tail latched comparator using negative body biasing that is more suitable in contraption of ECG cardiac signal monitoring. The new circuit is drawn and simulated in Mentor graphics EDA tool 180nm technology at applied voltage 0.8V. The simulation result offered favorable performance parameters in terms of total power and power delay product. The dissipated power of designed comparator is reduced from 18.5 PW to 12.5 PW at operating clock frequency 20 KHz, and it also gives reduced power delay product of 0.251aJ on 27 □ temperature.