Ternary Middle Value Decoder (T-MVD) on 90nm CMOS Technology

Identifying the middle value "1" of a ternary digit (trit) among 3-valued symbols "0", "1" and "2" is a major factor in most of the Ternary-based system design. This paper explores the circuit concept with working principle that can distinguish trit value "1" from others. The complete circuit has been designed on TSMC 90nm CMOS technology using BSIM4 device parameters with 1.0V supply rail at 27°C temperature. Ternary-digits "0", "1" and "2" are denoted by 0V, 0.5V and 1.0V respectively. The designed circuit has been validated through extensive T-Spice simulations with all possible test patterns using PWL data source. As per T-Spice simulation results the designed circuit dissipates 22.02µW average power with 0.22ns propagation delay.