An Accurate Structure Generation and Simulation of LER affected NWFET

Gate-All-Around (GAA) structures have shown great potential for replacing FinFETs in sub-10 nm technology node by facilitating a better gate control and improved short channel effects. Despite having an excellent gate control, the nanowire FETs (NWFETs) are prone to process-induced structural variability. Out of all, lithography and etching induced line edge roughness (LER) is one of the dominant sources of variability in sub 10 nm technology node GAA devices such as NWFET and nanosheet FET (NSFET). In this paper, we present a methodology to recreate an accurate NWFET surface morphology, where we generate NWFET surface profile using 2D ACF for a given LER variability parameters in MATLAB, and we incorporate the NWFET surface information in the Sentaurus Device Editor software using PERL interfacing to generate the final NWFET device structure. We generate 200 such random structures and simulate it all in a well-calibrated Sentaurus workbench deck. The proposed methodology can also be used to study the LER like variability in NSFET structures.