Alternative Reduced Hardware MASHI-I-I Digital Delta Sigma Architecture

This paper presents a modified structure of the digital accumulator, which provides the maximum cycle length of $(2^{n}+1)$. By using this structure Multistage noise shaping (MASHI-I-I) digital delta-sigma modulator (DDSM) is developed which yields the maximum cycle length of $(2^{n}+1)^{3}$ for most of the applied inputs, where n is the word length of the accumulator. The proposed MASHI-I-I architecture has been compared With the various existing MASHI-I-I architectures and shows a better performance in terms of noise shaping, input range and hardware consumption. Above performances have been shown by simulations, verified mathematically and digital gate counts.