Analyzing Hardware Security Properties of Processors through Model Checking

Security concerns are growing rapidly in the modern age of the widespread use of electronic products. Due to the increasing dependability on integrated circuits like processors, a security attack can lead to massive damages in different forms. Apart from software-based attacks, design errors in the hardware are also potential sources of security vulnerability. These kinds of vulnerabilities can be unlawfully utilized by attackers and malicious entities for causing damage to the users in different domains. However, discovering such threats is not trivial since simulation-based verification may fail to reveal such corner cases. In this paper, we investigate a formal approach for detecting hardware design errors which can lead to security vulnerabilities. By applying property checking with an industrial strength model checker (JasperGold), we investigate the design of different units of or1200 processor (5-stage pipeline design) for security threats. By an iterative refinement of properties, we were able to successfully write the security-critical properties of the processor through an understanding of the processor design manuals and specification documents. These properties are written in System Verilog Assertions (SVA) format and provided to the tool for model checking. When the properties fail, we obtain counter-examples that can be analyzed and studied for understanding the issues related to the secure operation of the processor. Model checking experiments were done for a total of thirteen security-critical properties. During our experiments, we also observed some security bugs related to the functionality of or 1200 processor design.