Verification Methodology of Vison Based Hardware Accelerators in System-on-Chip

The ever-shrinking process geometries and wide spread deployment of machine vision is pushing the boundaries of integration in System-on-Chips. The complexities of System-on-Chips are rapidly growing with demand for integration of more and more vision-based hardware accelerators into them. This poses several challenges in terms of verifying these vision-based hardware accelerators, in terms of not only functional specifications, but also their performance goals. The verification of vision-based hardware accelerators is often time consuming and at times even makes it impossible to ensure they meet their performance goals. This also poses serious challenge in terms of product time-to-market. This paper highlights a verification methodology, which can be deployed in vison-based hardware accelerators of System-on-Chip. This methodology focuses on faster and efficient ways of verifying vison-based hardware accelerators, including ways to measure their performance.