Study of optimized design of DDS based on FPGA

This paper introduces the design and implement of DDS based on FPGA. During the design process, the addressing way of ROM is proposed to improve the output frequency resolution. The optimization method called the compression method of ROM is advanced. The optimized design of NCO with different structures of accumulators (32 bits) including serial, parallel and pipelined is discussed. It is found that the pipeline (4 levels) accumulator has the biggest Fmax but consumes most LEs. There should be a balance between speed and resources during the design process. At last, DDS is implemented on ALTERA chip EP4CE15F17C8.