H3TRB Test on 6.5 kV SiC-JBS Diodes

In this work, the results of an H3TRB test on novel 6:5 kV SiC-JBS-Diodes are presented. The diodes under test feature an area of approximately 5 x 5 mm2 with a p-stripe JBS-design and a JTE-based edge-termination. The chips were covered with a globtop passivation and the substrates were afterwards potted with silicone gel. The test was terminated after approximately 1000 h. Visual inspection of the diodes revealed that some chips showed signs of degradation after the test at small spots at the top side metallization, the channel stopper and at the chips’ dicing edge. However, all chips passed over 1000 h of testing without any failure and no degradation of the electrical characteristics could be observed on any chip. Hence, SiC devices can be designed to be operated in harsh environments even for very high voltage classes.