A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications

This brief proposes a parallel path based strong-arm latch voltage comparator. The proposed architecture improves the speed performance when compared to the conventional strong-arm latch. The improvement is achieved by the addition of parallel paths to the output node. This increases the effective transconductance at the output node, allowing the load capacitor to discharge faster during the regenerative phase. The architecture has been designed and extensively simulated at pre- and post-layout level in a 65-nm CMOS technology with a supply voltage of 1 V and it achieves a 3-GHz bandwidth. The speed increases by approximately 50% with respect to the conventional topology. The Monte-Carlo analysis is performed for 200 samples, which results in an offset standard deviation of 2.05 mV.