Hybrid sorting algorithm implemented by High Level Synthesis

This paper proposes a hybrid data ordering algorithm which executes serial and parallel instructions. The implementation of the system is presented in the Zedboard development board of Xilinx that includes a SoC (System on Chip). The design was done in high level language HLS (High Level Synthesis). It receives a vector of N elements and delivers the set of indexes of the L major elements ordered. The complexity of the algorithm is analyzed in a generic way. The required times and resources are evaluated and compared with well known sorting algorithms.