Eight Bit Full Adder Design Using Fifteen Transistors With Novel Five Transistors XNOR Gate

Here, a new hybrid 8-bit full adder configuration utilizing both correlative metal-oxide-semiconductor (CMOS) reason and transmission gate judgment is described. The plan was first executed for 1 bit and after that stretched out for 32 bit likewise yet in this paper, the structure was actualized for 8-bit. The circuit was executed utilizing Cadence Virtuoso tools in 45-nm technology at 1.2-V and 1.8-V. Execution parameters for example power, delay, and transistor count up of the full adder contrasted and the officially existing paper. For 1.2-V supply at 45-nm technology, the normal power utilization 31.523nW was observed to be amazingly low with low defer 9.995ns resultant as of the predetermined inclusion of very frail CMOS inverters combined with well-built transmission gates designed for 1-bit. The plan was additionally stretched out for actualizing 8-bit full adder at 1.2-V (1.8-V) along with experimental towards only 241.0nW (556.1nW) power and −1.747ps (9.217ps) delay at 45-nm technology. Proposed full adder has been contrasted and the previously detailed circuits and the power utilization indicate better outcomes by enhancing XNOR gate.