Transition-delay Test Methodology for Designs with Self-gating

Power reduction is one of the most important design factors for system-on-chip. The self-gating method is used for power reduction in clock networks, which is one of the main factors of dynamic power consumption. However, scan test patterns can be increased by the self-gating insertion. It is observed that the test pattern increase is very severe for transition delay (TD) faults with the experimental results that over 250% of TD test patterns are increased with XOR selfgating insertion in the industrial circuits. In this paper, a new efficient TD test methodology is proposed which uses the data selectable self-gating (DSSG) structure. The experimental results show that using the new methodology, the average TD pattern increase ratio has dropped to under 50%.