Analysis and Monolithic Implementation of Differential Transimpedance Amplifiers

We present a comparison of design trade-offs for transimpedance, sensitivity, DC voltage offset cancellation, group-delay variation (GDV), common-mode rejection, and overload for transimpedance amplifiers (TIA) based on balanced, unbalanced, and pseudodifferential topologies. The TIAs are implemented monolithically in the IHP 250-nm SiGe BiCMOS EPIC process (fT = 190 GHz). Measurement results shown here support data rates to 50 Gb/s with BER better than 10
^-10
. The power consumption of the TIAs is 54 mW for TIA designs that approach 1 pJ/b.