MOS only voltage reference with improved line regulation for LDO voltage regulator applications

In this paper a voltage reference circuit using only MOSFETs in 180 nm standard CMOS technology is presented. The proposed circuit does not utilize lateral or vertical BJTs since they are not well defined in a CMOS technology, they occupy large area and they cause bulk current leakage. Complementary and proportional to absolute temperature currents are generated using MOSFETs, operating in sub-threshold region. An additional negative feedback is introduced so that line regulation of reference circuit is significantly improved. In LDO voltage regulators, the line regulation of LDO is mainly dependent on line sensitivity of reference circuit. The proposed voltage reference circuit has been laid out in standard 180 nm CMOS technology. The post layout simulation results show that it produces a reference voltage of 600 mV for a minimum input supply of 1.2 V. and varies only 1.2 mV when supply voltage is varied from 1.2 V to 2 V. When temperature is swept from 0 0 C to 80 0 C, the change in the reference voltage is only 4.1 mV. Monte-Carlo statistical analysis of the circuit reveals that it is robust against local mismatch and global process variations.