Analysis of 8-bit Vedic Multiplier using high speed CLA Adder

This research work proposes the vedic multiplier architecture with different carry lookahead adders like regular carry lookahead adder (RCLA), block carry lookahead adder (BCLA), factorized regular carry lookahead adder (FRCLA), factorized block carry lookahead adder (FBCLA). The vedic multipliers architecture was designed using ModelSim-Altera 6.3g (Quartus II 8.1) Web Edition and synthesized using Xilinx ISE Design suite. Initially the vedic multiplier was implemented using regular carry lookahead adder and replaced with other adders and the synthesis parameters were compared. After the comparison we have obsereved that the FRCLA is the best one interms of area and BCLA is the best one interms of delay.