Design and Analysis of Voltage Controlled Oscillators in 45nm CMOS Process

A Voltage Controlled Ring Oscillator, Current Starved Voltage Controlled Oscillator and Negative Skewed Oscillator are designed with system performance prioritized and layout drawn, considering their implementation in a Phase Locked Loop. Waveforms and parameters are compared at high performance and Layouts are designed with area under high priority. Layout Verification is done with Design Rule Check and Layout vs Schematic Assura quality checks. All the designs are implemented in 45nm technology node using gpdk45 technology Cadence Virtuoso System Design Platform.