Efficient Implementation of Recursive Multi-Frame Track-Before-Detect Algorithm Based on FPGA

It is widely recognized that the multi-frame Track-Before-Detect (MF-TBD) approaches show more advantages than the traditional Detect-Before-Track (DBT) approaches in the scene of weak targets detection and tracking. However, few studies focus on the engineering implementation of MF-TBD approaches in radar detection. Different from the traditional DBT approaches which only consider measurement points after single frame threshold detection, the implementation of MF-TBD approaches requires more transmission bandwidth and storage space. In this paper, we first analyzed the computational complexity of R-MF-TBD algorithm. Then the parallel processing architecture (PPA) was proposed to adapt the R-MF -TBD algorithm. Finally, we implemented the architecture for processing radar data on FPGA, and the correct tracks are output while the processing time is significantly lower than the software simulation.