Design and Analysis of Area and Power Optimised SRAM Cell for High-speed Processor

The basic 6T Static random access memory (SRAM) cell experience from relatively high static and total power loss problem, to solve this 8T, NC cells were designed. But this all consume more area as well as delay. Hence in this paper, 5T SRAM cell proposed and checked by Monte Carlo Simulation. The area reduced by 20.3%, 20.42%, and 7.82% compared to NC, 8T, and 6T cell respectively. The total power is reduced by 95.05%, 94.2%, and 96.6% compared to NC,8T, and 6T. Similarly, static power is diminished by 57.8%,75.8%, and 79.9% compared to NC, 8T, and 6T. Speed of proposed cell improved by 52.3%, 47.6%, and 53.9% compared to NC, 8T, and 6T respectively with acceptable stability. Finally, all the cells are also checked by Monte Carlo Simulation under 45 nm CMOS Technology.