Design of Optimum Nano Scale CMOS Inverter Integrated With RRAM

This work is concentrated on study of parameters which affect CMOS inverter switching speed. The switching speed is studied depending on the transient parameters which are the rise time and the fall time of an output pulse of the inverter. The transient parameters change according to design parameters of inverter like load capacitance, and channel width per length ratio. Three different studies have been performed to analyze the transient parameters of CMOS inverter. The output voltage fall time for a CMOS inverter is explored in first study. The design of CMOS inverter having symmetrical output voltage with equal rise time and fall time is described in second study. A CMOS inverter with improved symmetrical output voltage with equal rise time and fall time and equal delays when switching from high to low and when switching from low to high is explored in third study. A vision of a hybrid device based on integrating CMOS inverter and RRAM is developed to put a step in the way of merging logic unit and non-volatile memory.