Optimization of Active Voltage Rectifier / Doubler Designed in 90 nm Technology

This paper presents the optimization and comparison of three RF-to-DC circuit designs based on voltage rectifiers/doublers for Energy harvester systems. The first design is a 2-stage Differential Drive Cross-Coupled (DDCC) rectifier, the second one is a DDCC rectifier cascaded with a modified DDCC using a body-biasing technique for both NMOS and PMOS transistors and the third design is a DDCC using 2 pair of access transistors. These designs were simulated (TCAD Synopsys) in 90 nm CMOS Technology with three different output resistances ranging from 50, to 500 kΩ. Power (PCE) and voltage (VCE) conversion efficiencies were extracted and compared at a relatively high frequency (950MHz). The results show that after optimization for PCE, for all resistive loads used the DDCC with and without body biasing reach the best PCE% (70%) making these circuits good full wave rectifiers. However, design three gets the best VCE, enabling to properly duplicate the input voltage as required of any voltage doubler circuit.