An Area Efficient Low Phase Noise Charge Pump for PLL Applications in 90nm CMOS

This paper presents an area efficient and low phase noise charge pump in 90nm CMOS technology. The non-linearity effects of conventional charge pump are endeavored to improve in this model. Instead of using an op-amp, the cascade technique is applied to reduce current mismatch, whose performance is analyzed using temperature swept analysis, process corner analysis and Monte Carlo analysis. The proposed charge pump occupied 27.04μm² silicon area in layout design with de power consumption 34.0965 μW from the supply voltage of 1V. Finally, comparing with the state-of-art, the presented charge pump exposes a better performance in terms of low dc power consumption, low phase noise and less active layout area.