Increasing DDR4 SDRAM throughput in parallel workloads

DRAM chips and modules have been essential building blocks of electronic equipment ranging from embedded systems to supercomputers for decades. However, the chip technology trends have created a gap between processor and memory performance, aggravated by multi-core processor design. Not only memory bandwidth becomes insufficient in various applications, the actual throughput, or efficiency, of the memory is reduced in multi-threaded applications. In this work, we analyze the memory efficiency problem in parallel workloads, identify two approaches to solving it, survey and assess some of the possible solutions. In our experiments with DDR4 SDRAM controller, we achieve the average efficiency of 71 percent in 16-threaded workloads.