Impact Modeling of Single Ionizing Particles on the CMOS Triple Majority Gate

Results of modeling 65 nm CMOS the Triple Majority Gate on AND and OR logical elements for redundant systems are presented. The AND and OR elements contain inverters located before and after transistors of their NAND and NOR elements. This reduces the duration of the noise pulses when exposed to single ionizing particles. TCAD simulations use particle tracks passing along the normal to the chip crystal surface. With a linear energy transfer of 60 MeV-cm2/mg, the reduction in the pulse duration of noise at the output of CMOS AND (OR) gates is from 2 to 5 times.