12.4 A 700mW 4-to-1 SiGe BiCMOS 100GS/s Analog Time-Interleaver

Future 100Gbaud DSP-enabled optical coherent transceivers [1] will need 100GS/s DACs with an analog bandwidth (BW) of at least 50GHz to support advanced modulation schemes. CMOS-based DACs are preferred because they support monolithic integration of the DSP and DAC, but the achievable sampling rate and BW is limited [2]. To increase the sampling rate, multiple DACs can be passively or actively combined. A passive combiner using a distributed topology [3] increases the DAC sampling rate to 100GS/s with an analog BW of 13GHz. A 200GS/s linear active combiner with 44GHz analog BW is demonstrated in [4] using a bipolar process. Such linear combiner schemes [3], [4] extend their spurious-free dynamic range by adding the outputs of two complementary clocked DACs and cancelling the images in the even Nyquist zones, however, fundamentally their output analog BW cannot extend beyond the Nyquist frequency of the sub-DACs. Alternatively, time domain interleaving of DACs can be used. A 2-to-1 analog multiplexer (AMUX) using 130nm SiGe BiCMOS is reported in [5] with an analog BW >67GHz. Its measured sampling rate is 56GS/s. The 2-to-1 AMUX from [6] achieved>110GHz analog BW at 180GS/s using a 0.25μm InP HBT process, however it requires digital pre-processing to compensate the limited switching speed [7]. We report a 4-to-1 interleaver with an analog BW beyond Nyquist at sampling rates up to 100GS/s using SiGe BiCMOS. The interleaver is based on the generation and summation of return-to-zero (RZ) signals from analog input signals. The advantage of the architecture is that it can simultaneously perform equalization to e.g. compensate interconnect losses at its output and cancels clock feedthrough.