A 90-nm CMOS Low-Energy Dual-Channel Serial/Parallel Multiplier

This paper presents an integrated 90-nm CMOS low-energy dual-channel multiplier based on the serial/parallel scheme. Moreover, a comparative study of different multipliers is accomplished at 90 nm CMOS technology. Due to the tendency of the market to minimize devices' size to make them portable, small implementation area is considered by using the dual-channel multiplier. In this paper, a new implementation of multiplication process comes to exceed the battery lifetime by decreasing the power consumption by up to 93%. Furthermore, there is a reduction in the area by up to 67% as compared with previous work which makes it more appropriate for low power handheld devices applications. Also, great saving in energy is attained by using the proposed scheme when performing complex multiplications task.