Novel Bit-Reordering Circuit for Continuous-Flow Parallel FFT Architectures

This brief presents a parallel bit-reordering circuit for calculating bit reordering on a stream of parallel data. The circuit consists of buffers, multiplexers, a bit-reversal circuit for single path serial data, and control signal generators. A novel data reordering mechanism has been devised that has twofold benefits: firstly, it helps in attaining continuous flow of data with minimum memory and minimum latency; secondly, the area and power requirement of the circuit reduces by 15-20%. The proposed circuit provides a solution for reordering the data of different common radices such as radix-2^k, radix-4, radix-8, and other radices. The circuit generates natural order output for variable power-of-2 (2ⁿ) fast Fourier transform (FFT) lengths.