Design of Self-Biased LVDS Receiver for DAC in High Speed DDS Systems

A Low Voltage Differential Signal (LVDS) receiver with self-bias circuit for DAC of DDS system is presented in the paper. The circuit achieved in SMIC 180 nm standard CMOS process, and simulation results indicate that the proposed LVDS receiver is suitable for IEEE LVDS protocol. The circuit occupies a die area of 49 μm * 22 μm, and consumes a power of 0.326 mW from 1.8 V supply with 500 MS/s sampling rate. Meanwhile, RMS jitter is only 15 ps by the eye diagram simulation. It has been confirmed that the circuit is suitable for high speed DACs.