Designing of AES Algorithm using Verilog

One of most popular algorithm of cryptography is AES, which has data block of 16bytes and key size is variable of 128bits, 192bits and 256bits. In proposed design, AES method implemented by the use of Verilog using Xilinx ISE 14.7, which reduces operation time and clock cycles needed for encode and decode the message, if compared with implementation using VHDL. AES has more private compared with DES, because of its key size. It includes two main modules, in which all the sub modules are called by module call method. In application of embedded system it improves security measures.